This invention relates to semiconductor memory devices and method of manufacture, and more particularly to an electrically progammable read only memory (EPROM) of the floating gate type.
Nonvolatile memory devices using a floating gate to retain charge are made by a double level polysilicon process as set forth in U.S. Pat. No. 4,122,544 issued to David J. McElroy and U.S. Pat. No. 4,112,509 issued to Lawrence S. Wall, both assigned to Texas Instruments, or in U.S. Pat. No. 3,984,822 issued to Simko et al. These devices are widely used in microcomputers, particularly in program development.
The cell size in prior floating gate EPROMs has been large due to the metal to polysilicon contacts needed for each cell or cell pair, and due to the excess overlap of the control gate over the floating gate needed to provide a larger control gate to floating gate capacitance then floating gate to source-drain capacitance and to assure proper alignment. These features were necessary because of the process used for manufacture. Smaller cell size is desirable in order to provide a more dense array with more cells in a given silicon area, and/or to lower cost and increase yields in manufacture.
It is the principal object of this invention to provide an improved electrically programmable memory. Another object is to provide an EPROM of reduced cell size. An additional object is to provide a dense array of EPROM cells, made by a more efficient method.